The present invention relates to word lines of a semiconductor memory device, more particularly, to a layout method of the semiconductor memory array for reducing word line coupling noise and coupling capacitance between the word lines.
Memory elements or cells of the semiconductor memory device are influenced by the problems which are caused by the layout of higher packing cells memory array, because the semiconductor memory device tends to higher and higher packing cells memory circuit in a minute chip area.
Particularly, in the memory cell array having a plurality of bit lines and a plurality of word lines, narrower pitch between the lines because of its tendency to higher packing cells memory circuit, brings about capacitive couplings between the lines when a signal is transmitted through a line. The capacitive coupling between the lines is doubled by the capacitive component of line itself.
The larger the capacity of the semiconductor memory device is, the longer the length of the word line is, and the narrower the pitch between the word lines is.
However, since the time required to access the memory cell depends upon the length of the word line, the longer word line is undesirable. Accordingly, to compensate for the access time delay, metal layer is formed on polysilicon which is the matter of the word line, so that high speed operation has been possible. Coating the word lines with the metal causes the capacitive coupling between the lines to be larger due to the narrower pitch between the lines.
In other words, noise due to capacitive coupling between the metals is added to noise due to capacitive coupling between lines. Because such noise due to capacitive coupling between the word lines is charged or discharged in case that one word line is selected, this makes it possible to guide a wrong memory operation in high speed operation.
Of course, since miniaturization of the metal oxide semiconductor transistor cell and minutely scaled layout of the memory array according to higher packing cells memory circuit has high level driving voltage to drive the word lines, it is unable to neglect the noise due to the high level driving voltage. Therefore, the method that the driving voltage to drive the word line is lowered to less than 5 volts is adopted in order to remove this noise, but since the transistor requires its own threshold voltage to be operated, the method to lower the driving voltage to drive word line is limited.
The conventional memory array having several problems described above is illustrated in FIG. 1. Referring to FIG. 1, a plurality of bit lines BL.sub.l -BL.sub.j, a plurality of word lines is arranged across the bit lines, and each pair of bit lines is connected to each sense amplifiers. The memory cells are arranged on the crossing points of the word lines and the bit lines, the memory of the present invention has folded bit lines. In read operation of the memory device, the information being stored in the cell selected by the word line is loaded on the selected bit line, and then sense amplifier selected by the bit line reads the information. At this time, the coupling capacitance between the selected word line and the neighboring word line is illustrated in FIG. 3A. Referring to FIG. 3A, capacitive components will be described according to the memory array of FIG. 1. Coupling capacitances C.sub.12, C.sub.23, C.sub.34, C.sub.45 between the word lines WL.sub.1 -WL.sub.4, and substrate capacitances C.sub.1, C.sub.2, C.sub.3, C.sub.4 of the word lines WL.sub. 1 -WL.sub.4 are presented. Therefore, in case that any word line is selected, the voltage of word line coupling noise is: ##EQU1## (V.sub.WL : driving voltage of the selected word line) The substrate capacitance Cs of the word line depends on the metal formation of the word line and on the character of the substrate, so that the substrate capacitance Cs may be regarded as the constant. The driving voltage V.sub.WL of the word line is the factor to effect the word line coupling noise, but since the driving voltage for driving the word line is at most threshold voltage of the memory cell transistor, the term V.sub.WL is neglectable. Therefore, it can be easily understood by the skilled person in the art that the important factor to effect the word line coupling noise is the coupling capacitance Cc.